CVE-2025-56301 Other in n/a
Attackers can corrupt exception handling and privilege states in Rocket-Chip RISC-V cores via flawed CSR logic during MRET execution, potentially leading to privilege escalation.
- Exploited in the wild
- Not known
- Login needed
- Not needed
- Attackable
- Over the internet
- Victim action needed
- Not needed
- Fix
- None listed
What is CVE-2025-56301?
CVE-2025-56301 is a high-severity vulnerability in n/a, published on 30 Sep 2025. An attacker can exploit it over the internet without logging in, with no action from the victim.
Official description
An issue was discovered in Chipsalliance Rocket-Chip commit f517abbf41abb65cea37421d3559f9739efd00a9 (2025-01-29) allowing attackers to corrupt exception handling and privilege state transitions via a flawed interaction between exception handling and MRET return mechanisms in the CSR logic when an exception is triggered during MRET execution. The Control and Status Register (CSR) logic has a flawed interaction between exception handling and exception return (MRET) mechanisms which can cause faulty trap behavior. When the MRET instruction is executed in machine mode without being in an exception state, an Instruction Access Fault may be triggered. This results in both the exception handling logic and the exception return logic activating simultaneously, leading to conflicting updates to the control and status registers.
Weakness: CWE-1281
Which versions are affected by CVE-2025-56301?
It affects 1 product.
Products include Chipsalliance Rocket-Chip.
How do I fix CVE-2025-56301?
No fix has been published for CVE-2025-56301 yet. Limit exposure of the affected software until one is available.
Is CVE-2025-56301 being exploited?
There is no known exploitation of CVE-2025-56301 in the wild and no public exploit code.
Sources
Also known as GHSA-xgcq-34qv-mmr7.